Department of Computer Science

PDP-11 Processor Handbook

Addressing Modes


In the PDP-11 family, all operand addressing is accomplished through the general purpose registers. To specify the location of data (an operand address), one of eight registers is selected with an accompanying addressing mode. Each instruction specifies the: The instruction format and addressing techniques available to the programmer are of particular importance. This combination of addressing modes and the instruction set provides the PDP-11 family with a unique number of capabilities. The PDP-11 is designed to handle structured data efficiently and with flexibility. The general purpose registers implement these functions in the following ways, by acting: Using registers for both data manipulation and address calculation results in a variable length instruction format. If registers alone are used to specify the data source and destination, only one memory word is required to hold the instruction. In certain modes, two or three words may be utilized to hold the basic instruction components. Special addressing mode combinations enable temporary data storage for convenient dynamic handling of frequently accessed data. This is known as stack-addressing. Register 6 is always used as the hardware stack pointer, or SP. Register 7 is used by the processor as its program counter (PC). Thus, the register arrangement to be considered in conjunction with instructions and with addressing modes is: registers 0-5 are general purpose registers, register 6 is the hardware stack pointer, and register 7 is the program counter.

To illustrate the use of the various addressing modes clearly, the following instructions are used in this chapter:
MnemonicDescriptionOctal Code
CLRClear (Zero the specified destination word).0050DD
CLRBClear Byte (Zero the specified destination byte).1050DD
INCIncrement (Add one to contents of destination word).0052DD
INCBIncrement Byte (Add one to the contents of the destination byte).1052DD
COMComplement (Replace the contents of the destination by its logical one's complement. Each 0 bit is set and each 1 bit is cleared).0051DD
COMBComplement Byte (Replace the contents of the destination byte by its logical one's complement. Each 0 bit is set and each 1 bit is cleared).1051DD
ADDAdd (Add the source operand to the destination operand and store the results at the destination address).

Single- and double-operand instructions use the following formats. The instruction format for the first word of all single-operand instructions (such as clear, increment, test) is:

Single-Operand Instruction Format

Bits 5:3 of the destination field specify the binary code of the addressing mode chosen. Bits 2:0 specify the general register to be used.

The instruction format for the first word of the double-operand instruction is:

Double-Operand Instruction Format

Bits 11:9 of the source or 5:3 of the destination fields specify the binary code of the addressing mode chosen. Bits 8:6 and 2:0 specify the general register to be used.

The four basic addressing modes are:

In a register mode, the content of the selected register is taken as the operand. In autodecrement mode, after the register has been modified, it contains the address of the operand. In autoincrement mode, at the start of the instruction execution, the register contains the address of the operand, and, after the instruction is executed, the address of the next higher word or byte memory location. In index mode, the register is added to the displacement, X, to produce the address of the operand.

When bit 3 of the source/destination field is set, indirect addressing is specified and the four basic modes become deferred modes.

Prefacing the register operand(s) with an "@" sign or placing the register in parentheses indicates to the MACRO-11 assembler that deferred (or indirect) addressing mode is being used.

The indirect addressing modes are:

Program counter (register 7) addressing modes are: The addressing modes are explained and shown in examples in the following pages. They are summarized, in text and in graphic representation, at the end of the chapter.


REGISTER MODE MODE 0 Rn
Register mode provides faster instruction execution. There is no need to reference memory to retrieve an operand. Any of the general registers can be used as a simple accumulator. The operand is contained in the selected register (low-order byte for byte operation). Some assemblers require that a general register be defined as follows:

R0 = %0
R1 = %1
R2 = %2
% indicates register definition (as originally known to the assembler).

Register Mode Example

SymbolicInstruction
Octal Code
Description
INC R3005203Add one to the contents of R3
Represented as:

Register Mode Example

SymbolicInstruction
Octal Code
Description
ADD R2,R4060204 Add the contents of R2 to the contents of R4, replacing the original contents of R4 with the sum.
Represented as:


REGISTER DEFERRED MODE MODE 1 @Rn or (Rn)
In register deferred mode, the address of the operand is stored in a general purpose register. The address contained in the general purpose register. The address contained in the general purpose register directs the CPU to the operand. The operand is located outside the CPU's general purpose registers, either in memory or in an I/O register.

This mode is used for sequential lists, indirect pointers in data structures, top-of-stack manipulations, and jump tables.

Register Deferred Mode Example

SymbolicInstruction
Octal Code
Description
CLR (R5)005015 The Contents of the location specified in R5 are cleared.
Represented as:


AUTOINCREMENT MODE MODE 2 (Rn)+
In autoincrement mode, the register contains the address of the operand; the address is automatically incremented after the operand is retrieved. The address then references the next sequential operand. This mode allows automatic stepping through a list or series of operands stored in consecutive locations. When an instruction calls for mode 2, the address stored in the register is incremented each time the instruction is executed. It is incremented by one if you are using byte instructions, by two if you are using word instructions. However, R6 and R7 are always incremented by two.

To make it easy to remember that the register is incremented after use, the + sign follows the register name.

Autoincrement Mode Example

SymbolicInstruction
Octal Code
Description
CLR (R5)+005025 Contents of R5 are used as the address of the operand. Clear selected operand and then increment the contents of R5 by two.
Represented as:


AUTOINCREMENT DEFERRED MODE MODE 3 @(Rn)+
In autoincrement deferred mode, the register contains a pointer to the address of the operand. The + indicates that the pointer in Rn is incremented by two (for both word and byte operations) after the address is located. Mode 2, autoincrement, is used only to access operands that are stored in consecutive locations. Mode 3, autoincrement deferred, is used to access lists of operands stored anywhere in the system, i.e., the operands do not have to reside in adjoining locations. Mode 2 is used to step through a table of addresses that point to data.

Autoincrement Deferred Example

SymbolicInstruction
Octal Code
Description
INC @(R2)+005232 Contents of R2 are used as the address of the operand. The operand is increased by one, contents of R2 are incremented by two.
Represented as:


AUTODECREMENT MODE MODE 4 -(Rn)
In autodecrement mode, the register contains an address that is automatically decremented; the decremented address is used to locate an operand. This mode is similar to autoincrement mode, but allows stepping through a list of words or bytes in revers order. The address is decremented by one for bytes, by two for words. However, R6 and R7 are always decremented by two.

To remind you that the register is decremented prior to use, the - sign precedes the register name.

Autodecrement Mode Example

SymbolicInstruction
Octal Code
Description
INCB -(R0)105240 The contents of R0 are decremented by one, then used as the address of the operand. The operand byte is increased by one.
Represented as:


AUTODECREMENT DEFERRED MODE MODE 5 @-(Rn)
In autodecrement deferred mode, the register contains a pointer to the address of the operand. The pointer is first decremented by two (for both word and byte operations), then the new pointer is used to retrieve an address stored outside the CPU's general purpose registers. This mode is similar to autoincrement deferred, but allows stepping through a table of addresses in revers order. Each address then redirects the CPU to an operand. Note that the operands do not have to reside in consecutive locations.

Autodecrement Deferred Mode Example

SymbolicInstruction
Octal Code
Description
COM @-(R0)005150 The contents of R0 are decremented by two and then used as the address of the operand. The operand is one's complemented.
Represented as:


INDEX MODE MODE 6 X(Rn)
In index mode, a base address is added to an index word to produce the effective address of an operand; the base address specifies the starting location of table or list. The index word then represents the address of an entry in the table or list relative to the starting (base) address. The base address may be stored in a register. In this case, the index word follows the current instruction. Or the locations of the base address and index word may be reversed (index word in the register, base address following the current instruction).

Index Mode Example

SymbolicInstruction
Octal Code
Description
CLR 200(R4)005064
000200
The address of the operand is determined by adding 200 to the contents of R4. The resulting location is then cleared.
Represented as:


INDEX DEFERRED MODE MODE 7 @X(Rn)
In index deferred mode, a base address is added to an index word. The result is a pointer to an address, rather than the actual address. This mode is similar to mode 6, except that it produces a pointer to an address. The content of that address then redirects the CPU to the desired operand. Mode 7 provides for the random access of operands using a table of operand addresses.

Index Deferred Mode Example

SymbolicInstruction
Octal Code
Description
ADD @1000(R2),R1067201
001000
1000 and the contents of R2 are summed to produce the address of the address of the source operand, the contents of which are added to the contents of R1. The result is stored in R1.
Represented as:


Use of the PC as a General Register

Register 7 is both a general purpose register and the program counter on the PDP-11. When the CPU uses the PC to access a word from memory, the PC is automatically incremented by two to contain the address of the next word of the instruction to be executed or the address of the next instruction to be executed. When the program uses the PC to access byte data, the PC is still incremented by two.

The PC can be used with all of the PDP-11 addressing modes. There are four modes in which the PC can provide advantages for handling position-independent code and for handling unstructured data. These modes refer to the PC and are termed immediate, absolute (or immediate deferred), relative, and relative deferred. The respective 6-bit octal codes are 27, 37, 67 and 77.

Note that the other 4 modes having octal codes 07, 17, 47 and 57 should be avoided by the assembly language programmer. Their respective operand syntaxes (to be avoided) would be PC, (PC) or @PC, -(PC), and @-(PC).


PC IMMEDIATE MODE MODE 2 #n
Immediate mode is equivalent to using the autoincrement mode with the PC. It provides time improvements for accessing constant operands by including the constant in the memory location immediately following the instruction word.

PC Immediate Mode Example

SymbolicInstruction
Octal Code
Description
ADD #10,R0062700
000010
The value 10 is located in the second word of the instruction and is added to the contents of R0. Just before this instruction is fetched and executed, the PC points to the first word of the instruction. The processor fetches the first word and increments the PC by two. The source operand mode is 27 (autoincrement the PC). Thus, the PC is used as a pointer to fetch the operand (the second word of the instruction) before being incremented by two to point to the next instruction.
Represented as:


PC ABSOLUTE MODE MODE 3 @#a
This mode is the equivalent of immediate deferred or autoincrement deferred mode using the PC. The contents of the location following the instruction are taken as the address of the operand. Immediate data are interpreted as an absolute address (i.e., an address that remains constant no matter where in memory the assembled instruction is executed).

PC Absolute Mode Example

SymbolicInstruction
Octal Code
Description
CLR @#1100005037
001100
Clears the contents of location 1100.
Represented as:


PC RELATIVE MODE MODE 6 X(PC)
or A
This mode is index mode 6 using the PC. The operand's address is calculated by adding the word that follows the instruction (called an "offset") to the updated contents of the PC.

PC + 2 directs the CPU to the offset that follows the instruction. PC + 4 is summed with this offset to produce the effective address of the operand. PC + 4 also represents the address of the next instruction in the program.

With the relatvie addressing mode, the address of the operand is always determined with respect to the updated PC. Therefore, if the entire program is relocated, the oeprand remains the same relative distance away and may be accessed with changing the instruction.

The distance between the updated PC and the operand is called an offset. After a program is assembled, this offset appears in the first word location that follows the instruction. This mode is useful for writing position-independent code. It is the default mode generated by the MACRO assembler.

PC Relative Mode Example

SymbolicInstruction
Octal Code
Description
INC A005267
000054
To increment A, the contents of the memory location in the second word of the instruction are added to the updated PC to produce the address of A (1100). The contents of A are increased by one.
Represented as:


PC RELATIVE DEFERRED MODE MODE 7 @X(PC) or
@A
This mode is index deferred (mode 7), using the PC. A pointer to an operand's address is calculated by adding an offset (which follows the instruction) to the updated PC.

This mode is similar to the relative mode, except that it involves one additional level of addressing to obtain the operand. The sum of the offset and updated PC (PC+4) serves as a pointer to an address. When the address is retrieved, it can be used to locate the operand.

PC Relative Deferred Mode Example

SymbolicInstruction
Octal Code
Description
CLR @A005077
000020
Adds the second word of the instruction to the updated PC to produce A - location 1044 - the address of the address of the operand. Clears operand.
Represented as:


Don S. Bidulock
Department of Computer Science
University of Calgary
Calgary, Alberta
Canada T2N 1N4
Phone: 403 220-7689 Fax: 403 284-4707
email: dsb@cpsc.ucalgary.ca

University of Calgary