Department of Computer Science

PDP-11 Processor Handbook

Program Control Instructions


The offset in a branch instruction is interpreted as an 8-bit signed integer defining a count of the number of words to the target address from the current value of PC (which is always 2 greater than the address of the branch instruction). This offset is multiplied by 2 to turn it into a byte count, which is then added to the PC if the branch is to be taken. Since the offset is a signed integer a branch may be taken in either a forward (up to +128 words) or backward (up to -127 words) direction from the address of the instruction.

The 6-bit offset in an SOB instruction, on the other hand, is interpreted as an unsigned integer defining the word count to the target address only in a backward direction. This branch cannot target an address that is further than 62 words backwards from the address of the SOB instruction.


BR 0 000 000 1xx xxx xxx
Operation:PC = PC + (2 * offset)
Condition Codes:Unaffected
Description:Provides a way of transferring program control within a range of -128 to +127 words with a one word instruction.

BEQ 0 000 001 1xx xxx xxx
Operation:PC = PC + (2 * offset) if Z = 1
Condition Codes:Unaffected
Description:Tests the state of the Z-bit and causes a branch if Z is set. As an example, it is used to test equality following a CMP operation, to test that no bits set in the destination were also set in the source following a BIT operation, and generally, to test that the result of the previous operation was zero.
Examples:
CMP A,B;compare A and B
BEQ C;branch if A is equal to B
 will branch to C if A == B, and the sequence
 
ADD A,B;compare A and B
BEQ C;branch if result equal to 0
 will branch to C if A+B == 0.

BNE 0 000 001 0xx xxx xxx
Operation:PC = PC + (2 * offset) if Z = 0
Condition Codes:Unaffected
Description:Tests the state of the Z-bit and causes a branch if the Z-bit is clear. BNE is the complementary operation to BEQ. It is used to test inequality following a CMP, to test that some bits set in the destination were also in the source, following a BIT, and generally, to test that the result of the previous operation was not zero.
Examples:
CMP A,B;compare A and B
BNE C;branch if A not equal to B
 will branch to C if A != B, and the sequence
 
ADD A,B;compare A and B
BNE C;branch if result not equal to 0
 will branch to C if A+B != 0.

BMI 1 000 000 1xx xxx xxx
Operation:PC = PC + (2 * offset) if N = 1
Condition Codes:Unaffected
Description:Tests the state of the N-bit and causes a branch if N is set. It is used to test the sign (most significant bit) of the result of the previous operation, branching if negative.

BPL 1 000 000 0xx xxx xxx
Operation:PC = PC + (2 * offset) if N = 0
Condition Codes:Unaffected
Description:Tests the state of the N-bit and causes a branch if N is clear. BPL is the complementary operation of BMI.

BCS 1 000 011 1xx xxx xxx
Operation:PC = PC + (2 * offset) if C = 1
Condition Codes:Unaffected
Description:Tests the state of the C-bit and causes a branch if C is set. It is used to test for a carry in the result of a previous operation.

BCC 1 000 011 0xx xxx xxx
Operation:PC = PC + (2 * offset) if C = 0
Condition Codes:Unaffected
Description:Tests the state of the C-bit and causes a branch if C is clear. BCC is the complementary operation to BCS

BVS 1 000 010 1xx xxx xxx
Operation:PC = PC + (2 * offset) if V = 1
Description:Tests the state of V bit (overflow) and causes a branch if the V bit is set. BVS is used to detect signed arithmetic overflow in the previous operation.

BVC 1 000 010 0xx xxx xxx
Operation:PC = PC + (2 * offset) if V = 0
Condition Codes:Unaffected
Description:Tests the state of the V bit and causes a branch if the V bit is clear. BVC is complementary operation to BVS.

BLT 0 000 010 1xx xxx xxx
Operation:PC = PC + (2 * offset) if N or V = 1
Condition Codes:Unaffected
Description:Causes a branch if the "Exclusive Or" of the N and V bits are 1. Thus BLT will always branch following an operation that added two negative numbers, even if overflow occurred. In particular, BLT will always cause a branch if it follows a CMP instruction operating on a negative source and a positive destination (even if overflow occurred). Further, BLT will never cause a branch when it follows a CMP instruction operating on a positive source and negative destination. BLT will not cause a branch if the result of the previous operation was zero (without overflow).

BGE 0 000 010 0xx xxx xxx
Operation:PC = PC + (2 * offset) if N or V = 0
Condition Codes:Unaffected
Description:Causes a branch if N and V are either both clear or both set. BGE is the complementary operation to BLT. Thus BGE will always cause a branch when it follows an operation that caused addition of two positive numbers. BGE will also cause a branch on a zero result.

BLE 0 000 011 1xx xxx xxx
Operation:PC = PC + (2 * offset) if Z or(N xor V) = 1
Condition Codes:Unaffected
Description:Operation is similar to BLT but in addition will cause a branch if the resul of the previous operation was zero.

BGT 0 000 011 0xx xxx xxx
Operation:PC = PC + (2 * offset) if Z or(N xor V) = 0
Condition Codes:Unaffected
Description:Operation of BGT is similar to BGE, except BGT will not cause a branch on a zero result.

BHI 1 000 001 0xx xxx xxx
Operation:PC = PC + (2 * offset) if C = 0 and Z = 0
Condition Codes:Unaffected
Description:Causes a branch if the previous operation caused neither a carry nor a zero result. This will happen in comparison (CMP) operations as long as the source has a higher unsigned value than the destination.

BLOS 1 000 001 1xx xxx xxx
Operation:PC = PC + (2 * offset) if C or Z = 1
Condition Codes:Unaffected
Description:Causes a branch if the previous operation caused either a carry or a zero result. BLOS is the complementary operation to BHI. The branch will occur in comparison operations as long as the source is equal to, or has a lower unsigned value than the destination.

BLO 1 000 011 1xx xxx xxx
Operation:PC = PC + (2 * offset) if C = 1
Condition Codes:Unaffected
Description:BLO is the same instruction as BCS. This mnemonic is included only for convenience, used instead of BCS when performing unsigned comparisons, for documentation purposes.

BHIS 1 000 011 0xx xxx xxx
Operation:PC = PC + (2 * offset) if C = 0
Condition Codes:Unaffected
Description:BHIS is the same instruction as BCC. This mnemonic is included only for convenience, used instead of BCC when performing unsigned comparisons, for documentation purposes.

SOB 0 111 111 rrr xxx xxx
Operation:R = R-1, if this result != 0 then PC = PC - (2 * offset)
Condition Codes:Unaffected
Description:The register is decremented. If it is not equal to 0, twice the offset is subtracted from the PC (now pointing to the following word). The offset is interpreted as a six bit unsigned (positive) number. This instruction provides a fast, efficient method of loop control. Assembler syntax is:

SOB R,A

Where A is the address to which transfer is to be made if the decremented R is not equal to 0. Note that the SOB instruction can not be used to transfer control in a forward direction.

Note: in the PDP-11/60, the SOB instruction may require more time than the sequence
DEC R
BNE
See Appendix B for timing information.

JMP 0 000 000 001 ddd ddd
Operation:PC = dest
Condition Codes:Unaffected
Description:JMP provides more flexible program branching than provided with the branch instructions. Control may be transferred to any location in memory (no range limitation) and can be accomplished with the full flexibility of the addressing modes, with the exception of register mode 0. Execution of a jump with mode 0 will cause an "illegal" instruciton condition and results in a processor trap through the trap vector address 4 (program control cannot be transferred to the address of a register). Register deferred mode is legal and will cause program control to be transferred to the address held in the specified register. Note that instructions are word data and must therefore be fetched from an even-numbered address. A "boundary error" trap condition will result when the processor attempts to fetch an instruction from an odd address.

Deferred index mode JMP instructions permit transfer of control to the address contained in a selectable element of a table of dispatch vectors. This is commonly called a "jump table".

JSR 0 000 100 rrr ddd ddd
Operation:temp = dest (temp is an internal processor register)

-(SP) = reg (push reg contents onto processor stack)

reg = PC (PC holds location following JSR; this address now put in reg)

PC = temp (PC now points to subroutine address)
Condition Codes:Unaffected
Description:In execution of the JSR, the old contents of the specified register (the "Linkage Register") are automatically pushed onto the processor stack and new linkage information placed in the register. Thus subroutines nested within subroutines to any depth may all be called with the same linkage register. There is no need either to plan the maximum depth at which any particular subroutine will be called or to include instructions in each routine to save and restore the linkage pointer. Further, since all linkages are saved in a reentrant manner on the processor stack, execution of a subroutine reentered and executed by an interrupt service routine. Execution of the initial subroutine can then be resumed when other requests are satisfied. This process (called nesting) can proceed to any level.

In both JSR and JMP instructions the destination address is used to load the program counter, R7. Thus for example a JSR in destination mode 1 for general register R1 (where (R1) = 100), will access a subroutine at location 100. This is effectively one level less of deferral than operate instructions such as ADD.

In the PDP-11/60, a JSR using addressing mode 0 will result in an "illegal" instruction and a trap through the trap vector address 4.

A subroutine called with a JSR reg,dest instruction can access the arguments following the call with either autoincrement addressing, (reg) +, (if arguments are accessed sequentially) or by indexed addressing, X(reg), (if accessed in random order). These addressing modes may also be deferred, @(reg) + and @X(reg) if the parameters are operand addresses rather than the operand themselves.

JSR PC,dest is a special case of the PDP-11 subroutine call suitable for subroutine calls that transmit parameters through the general registers or on the system stack. The SP and the PC are the only registers that may be modified by this call.

Another special case of the JSR instruction is JSR PC,@(SP) + which exchanges the top element of the processor stack and the contents of the program counter. Use of this instruction allows two routines to swap program control and resume operation when recalled where they left off. Such routines are called "co-routines."

Return from a subroutine is done by the RTS instruction. RTS reg loads the contents of reg into the PC and pops the top element of the processor stack into the specified register.

RTS 0 000 000 010 000 rrr
Operation:PC = reg
reg = (SP)+
Condition Codes:Unaffected
Description:Loads the contents of reg into PC and pops the top element of the processor stack into the specified register. Return from a non-reentrant subroutine is typically made through the same register that was used in its call. Thus, a subroutine called with a JSR PC,dest exits with a RTS PC and a subroutine called with a JSR R5,dest may retrieve parameters with addressing modes (R5)+, X(R5), or @X(R5), and finally exits with an RTS R5.

MARK 0 000 110 100 nnn nnn
Operation:SP = PX + 2xnn nn = number of parameters
PC = R5
R5 = (SP)+
Condition Codes:Unaffected
Description:Used as part of the standard PDP-11 subroutine return convention. MARK facilitates the stack clean up procedures involved in subroutine exit. Assembler format is MARK N.
Example: ;the subroutine ;put opcode code for MARK 3 on stack
MOV R5,-(SP) ;place old R5 on stack
MOV P1,-(SP) ;place 3 parameters on the
MOV P2,-(SP) ;stack to be used there by
MOV P3,-(SP)
MOV #6403,-(SP)
MOV SP,R5 ;set up pointer MARK 3 instruction
JSR PC,SUB ;jump to subroutine

At this point, after the call, the stack is as follows:

RETURN;stack top
006403;MARK 3
P3;parameter #3
P2;parameter #2
P1;parameter #1
OLD R5;stack bottom

Now execution control is in subroutine SUB having the code:

SUB: etc. ;execution of the subroutine itself
etc. 
RTS R5 ;the return instruction
Execution of the RTS causes the contents of R5 to be placed in the PC which then results in the execution of the instruction MARK 3. The contents of the RETURN address are placed in R5.

MARK 3 causes: (1) the stack pointer to be adjusted to point to the old R5 value;
(2) the value now in R5 (the RETURN address) to be placed in the PC; and
(3) the contents of the old R5 to be popped into R5 thus completing the return from the subroutine.

Note: If Memory Management is in use a stack must be in I and D spaces (Chapter 6) to execute the MARK instruction.

SPL 1 000 110 111 ddd ddd
Note:SPL is not implemented in the PDP-11/60. A processor trap through vector address 10 occurs for illegal instruction.

EMT 1 000 100 0xx xxx xxx
Operation:-(SP) = PS
-(SP) = PC
PC = (30)
PS = (32)
Condition Codes:N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector
Description:All operation codes from 104000 to 104377 are EMT instructions and may be used to transmit information to the emulating routine (e.g., function to be performed). The trap vector for EMT is at address 30. The new PC is taken from the word at address 30; the new central processor status (PS) is taken from the word at address 32.

Caution: EMT is used frequently by DIGITAL system sofware and is therefore not recommended for general use.

TRAP 1 000 100 1xx xxx xxx
Operation:-(SP) = PS
-(SP) = PC
PC = (34)
PS = (36)
Condition Codes:N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector
Description:Operation codes from 104400 to 104777 are TRAP instructions. TRAPs and EMTs are identical in operation, except that the trap vector for TRAP is at address 34.

Note: Since DEC software makes frequent use of EMT, the TRAP instruction is recommended for general use. TRAPs are used to implement system calls in Unix Operating Systems (see Unix command "man 2 intro").

BPT 0 000 000 000 000 011
Operation:-(SP) = PS
-(SP) = PC
PC = (14)
PS = (16)
Condition Codes:N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector
Description:Performs a trap seqence with a trap vector address of 14. Used to call debugging aids. The user is cautioned against employing code 000003 in programs run under these debugging aids (no information is transmitted in the low byte).

IOT 0 000 000 000 000 100
Operation:-(SP) = PS
-(SP) = PC
PC = (20)
PS = (22)
Condition Codes:N: loaded from trap vector
Z: loaded from trap vector
V: loaded from trap vector
C: loaded from trap vector
Description:Performs a trap sequence with a trap vector address of 20. Used to call the I/O Executive routine IOX in the paper tape software system, and for error reporting in the Disk Operating System (no information is transmitted in the low byte).

RTI 0 000 000 00 000 010
Operation:PC = (SP)+
PS = (SP)+
Condition Codes:N: loaded from processor stack
Z: loaded from processor stack
V: loaded from processor stack
C: loaded from processor stack
Description:Used to exit from an interrupt or TRAP service routine. The PC and PS are restored (popped) from the processor stack.

RTT 0 000 000 000 000 110
Operation:PC = (SP)+
PS = (SP)+
Condition Codes:N: loaded from processor stack
Z: loaded from processor stack
V: loaded from processor stack
C: loaded from processor stack
Description:This is the same as the RTI instruction except that it inhibits a trace trap, while RTI permits a trace trap. If a trace trap is pending, the first instruction after the RTT will be executed prior to the next "T" trap. In the case fo the RTI instruction the "T" trap will occur immediately after the RTI.

HALT 0 000 000 000 000 000
Condition Codes:Unaffected
Description:Causes the process operation to cease. The console is given control of the bus. The console data lights display the contents of PC. The PC points to the next instruction to be executed. Pressing the continue key on the console causes processor operation to resume. No INIT signal is given.

Note: a HALT issued in User Mode will generate a trap through vector address 10.

WAIT 0 000 000 000 000 001
Condition Codes:Unaffected
Description:Provides a way for the processor to relinquish use of the bus while it waits for an interrupt. Having been given a WAIT command, the processor will not compete for bus use by fetching instructions or operands from memory. This permits higher transfer rates between a device and memory, since no processor-induced latencies will be encountered by bus requests from the device. In WAIT, as in all instructions, the PC points to the next instruction following the WAIT operation. Thus when the service routine executes an RTI instruction, at the end of the routine, the program will resume at the instruction following the WAIT. Note also that Floating Point, Power Fail, and Parity Traps will cause the processor to fall through the WAIT loop.

Passive release of the bus will not cause the processor to fall through the WAIT loop. A passive release occurs when a device requests the bus, but never transmits an interrupt Vector when it receives a Bus Grant.

RESET 0 000 00 000 00 101
Condition Codes:Unaffected
Description:Sends INIT on the UNIBUS for 10 ms. All devices on the UNIBUS are reset to their state at power up.

In User Mode, the RESET instruction is treated as a no-op.

Within the PDP-11/60 processor, the Stack Limit and Memory Management Register, MMR0, are initialized.

MTPS 1 000 110 100 sss sss
Note:MTPS is not implemented in the PDP-11/60. A processor trap through vector address 10 occurs for reserved instruction.

MFPS 1 000 110 111 ddd ddd
Note:MFPS is not implemented in the PDP-11/60. A processor trap through vector address 10 occurs for reserved instruction.

NOP
CLNSEN
CLZSEZ
CLVSEV
CLCSEC 0 000 000 010 10N ZVC
CCCSCC 0 000 000 010 11N ZVC
Description:Set and clear condition code bits. Selectable combinations of these bits may be cleared or set together. Condition code bits corresponding to bits in the condition code operator (Bits 0-3) are modified according to the sense of bit 4, the set/clear bit of the operator. i.e. set the bit specified by bit 0, 1, 2 or 3, if bit 4 is a 1. Clear corresponding bits if bit 4 = 0.
 
MnemonicOperationOP Code
NOPNo Operation000240
CLCClear C000241
CLVClear V000242
CLZClear Z000244
CLNClear N000250
CCCClear all CCs000257
 No Operation000260
SECSet C000261
SEVSet V000262
SEZSet Z000264
SENSet N000270
SCCSet all CCs000277
 Combinations of the above set or clear operation codes may be ORed together to form combined instructions. For example:
 
Clear V and C000243
Set N and Z000274


Don S. Bidulock
Department of Computer Science
University of Calgary
Calgary, Alberta
Canada T2N 1N4
Phone: 403 220-7689 Fax: 403 284-4707
email: dsb@cpsc.ucalgary.ca

University of Calgary