## Extended Instruction Set (EIS)

 The assembler format for all EIS instructions excluding XOR is: OPR srce,R Here the register is (part of) the destination operand. However, the assembler format for XOR is: OPR R,dest Here the register contains the source operand.

 MUL 0 111 000 rrr sss sss
Operation:R,Rv1 = R * srce
Condition Codes: N: set if product is < 0; cleared otherwise
Z: set if product is 0; cleared otherwise
V: cleared
C: set if result is less than -2^15 or greater than or equal to 2^15-1
Description:The contents of the destination register and source taken as 16-bit two's complement integers are multiplied and stored as a 32-bit result in the destination register and the succeeding register if R is even. If an even register is specified the 32-bit product is stored with the high 16 bits in the even register and the low 16 bits in the odd register. If R is odd, only the low order 16 bits of the product is stored in the odd register. The condition codes are set according to the internally generated 32-bit product. Note that the actual destination is R,Rv1 which reduces to just R when R is odd, leaving the even numbered preceding register untouched.
Example:
 CLC ;Clear carry condition code MOV #400,R1 MUL #10,R1 16-bit product (R is odd), R0 untouched BCS ERROR Carry will be set if product is less than -2^15 or greater than or equal to 2^15-1, no significance lost Before: After: (R1)=000400 (R1)=004000

 DIV 0 111 001 rrr sss sss
Operation:R,Rv1 = R,Rv1 / srce, R = result, Rv1 = remainder
Condition Codes: N: set if quotient < 0; cleared otherwise, unless V is set, then undefined
Z: set if quotient = 0; cleared otherwise, unless V is set, then undefined
V: set if source = 0 or if the absolute value of the register is larger than the absolute value of the source (in this case the instruction is aborted because the quotient would exceed 15 bits), or set if the quotient results in the most negative number (100000) and the XOR of the signs of the operands = 0
C: set if divide 0 attempted; cleared otherwise
Description:The 32-bit two's complement integer in R and Rv1 is divided by the source operand. The quotient is left in R; the remainder in Rv1. Division will be performed so that the remainder is of the same sign as the dividend. R must be even.
Example:
 MOV #20001,R1 ;Define low order 16 bits SXT R0 ;Sign extend high order 16 bits DIV #2,R0 ;Divide 16-bit 2 into 32-bit R0,R1 Before: After: (R0)=000000 (R0)=010000 (R1)=020001 (R1)=000001

 ASH 0 111 010 rrr sss sss

Operation:R = R Shifted arithmetically N places to the right or left, where N = srce
Condition Codes: N: set if result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: set if sign of register changed during shift; cleared otherwise
C: loaded from last bit shifted out of register
Description:The contents of the register are shifted right or left the number of times specified by the source operand. The shift count is taken as the low order 6 bits of the source operand. This number ranges from -32 to +31. Negative is a right shift and positive is a left shift. For example, if the LSB 6 bits of the source are: 011111, then shift left 31 places; if 000001, then shift left 1 place; if 111111, then shift right 1 place; if 100000, then shift right 32 places.
Example:
 ASH R3,R0 Before: After: (R0)=001234 (R0)=012340 (R3)=000003 (R3)=000003 NZVC=1111 NZVC=0000

 ASHC 0 111 011 rrr sss sss

 Operation: R,Rv1 = R,Rv1, the double word is shifted N places to the right or left, where N = srce Condition Codes: N: set if result < 0; cleared otherwise Z: set if result = 0; cleared otherwise V: set if sign bit changes during the shift; cleared otherwise C: loaded with high order bit when left shift; loaded with low order bit when right shift (loaded with the last bit shifted out of the 32-bit operand) Description: The contents of the register pair R,Rv1 (R an even register, Rv1 an odd register) are treated as one 32 bit word, Rv1 containing bits 0 to 15, R bits 16 to 31, and are shifted right or left the number of times specified by the source operand. The source contains a shift count taken as the low order 6 bits of the operand. This number ranges from -32 to +31. Negative is a right shift and positive is a left shift. When the register chosen is an odd number, R and Rv1 are the same. In this case the right shift becomes a rotate. The 16 bit word is rotated right the number of bits specified by the shift count provided the count is less than or equal to 16. If an even register is specified the sign of the 32-bit operand is bit 15 of the shifted result of the even register. If an odd register is specified, the sign is bit 15 of the shifted result in the odd register.

 XOR 0 111 100 rrr ddd ddd
Operation:dest = R xor dest
Condition Codes: N: set if the result < 0; cleared otherwise
Z: set if result = 0; cleared otherwise
V: cleared
C: unaffected
Description:The "Exclusive OR" of the register and destination operand is stored in the destination. Contents of register are unaffected.
Example:
 XOR R0,R2 Before: After: (R0)=001234 (R0)=012340 (R2)=001111 (R2)=000325 NZVC=1111 NZVC=0001

Don S. Bidulock
Department of Computer Science
University of Calgary
Calgary, Alberta