Department of Computer Science

PDP-11 Processor Handbook

The PDP-11 Family Heirarchy


The Family Concept

The idea of a "family" of processors of varying capability with each family member possessing a common architecture but a different implementation is not new. The goal is software compatibility across all processors at the machine language level. The benefits of this are numerous. System software evolution continues and such hardware can generally be retrofitted to early family members at any time. Architectural shortcomings or ambiguities are recognized and rectified. Existing software may often be accelerated in performance simply by retiring one processor for another that utilizes more modern technology. Alternatively, newer memory technology may enhance software performance on the same processor. New system peripherals are developed to enhance the utility of existing processors and the huge user base of the common architecture gives rise to an enormous number of useful programs, many of which may be available at nominal cost from a central distribution point (e.g., the Digital Equipment Computer Users Society, DECUS, for the PDP-11).

Technological Implementations

The family concept has possibly seen its most widespread realization in the DEC PDP-11. For marketing purposes, the PDP-11 family is categorized into groups that allow industry to select a system appropriate for its need and affordability:

Figure 1-1

Since production of the PDP-11 in 1970, about 10 different implementations have appeared. These different models can be grouped into four different chronological "streams":

  1. Constant Price, Increasing Performance: 11/20 (1970); 11/40 (1972); 11/60 (1977).

  2. Decreasing Price, Constant Performance:

    • Series (i): 11/20 (1970); 11/05,10 (1973); 11/04 (1975); 11/03 (1975); PDT-11's (1978);

    • Series (ii): 11/40 (1972); 11/34 (1976); 11/23,24 (1979).

  3. Increasing Price, Substantially Increasing Performance: 11/20 (1970); 11/45 (1972); 11/70 (1974); 11/55 (1976); VAX-11/780 (1977).
"Price" implies minimum system cost and "performance" includes both speed and reliability considerations. A pictorial representation relating different models to price versus performance, combined with technological advancement, appears below:

Figure 1-3

Performance enhancement may be achieved by increasing processor execution speeds, by extending the architecture (e.g., floating point processor), or by enhancing memory performance (e.g., cache memory). For the PDP-11 the relevent enhancements were:

Compatibility

Since PDP-11 processors are upward compatible, both hardware and software are portable. The UNIBUS ensures that peripheral devices may be moved from one machine to another. The hardware capabalities of the various machines are summarized in the following table:

Feature11/0311/0411/05,1011/3411/35,4011/6011/45,70
General Registers8888/98/98,916
Memory Managementnononoyesyes(O)yesyes(O)
Processor Modes1112223
Extended ArithmeticEIS(O),FIS(O)EAE(O)EAE(O)EIS,FPP(O)EIS(O),FIS(O)EIS,FPPEIS,FPP(O)
Cache Memorynononoyesyesyesno(45),yes(70)
User Microprogrammableyes(O)nononoyes(O)yes(O)no
Register-to-Register Add3.5 us3.2 us3.7 us2.1 us1.0 us.34 us.30 us

The "O" designation in the above table means "Optional". The register-to-register add time in microseconds is indicative of processor speed.


Don S. Bidulock
Department of Computer Science
University of Calgary
Calgary, Alberta
Canada T2N 1N4
Phone: 403 220-7689 Fax: 403 284-4707
email: dsb@cpsc.ucalgary.ca

University of Calgary