The idea of a "family" of processors of varying capability with each family member possessing a common architecture but a different implementation is not new. The goal is software compatibility across all processors at the machine language level. The benefits of this are numerous. System software evolution continues and such hardware can generally be retrofitted to early family members at any time. Architectural shortcomings or ambiguities are recognized and rectified. Existing software may often be accelerated in performance simply by retiring one processor for another that utilizes more modern technology. Alternatively, newer memory technology may enhance software performance on the same processor. New system peripherals are developed to enhance the utility of existing processors and the huge user base of the common architecture gives rise to an enormous number of useful programs, many of which may be available at nominal cost from a central distribution point (e.g., the Digital Equipment Computer Users Society, DECUS, for the PDP-11).
The family concept has possibly seen its most widespread realization in the DEC PDP-11. For marketing purposes, the PDP-11 family is categorized into groups that allow industry to select a system appropriate for its need and affordability:
Since production of the PDP-11 in 1970, about 10 different implementations have appeared. These different models can be grouped into four different chronological "streams":
Performance enhancement may be achieved by increasing processor execution speeds, by extending the architecture (e.g., floating point processor), or by enhancing memory performance (e.g., cache memory). For the PDP-11 the relevent enhancements were:
Since PDP-11 processors are upward compatible, both hardware and software are portable. The UNIBUS ensures that peripheral devices may be moved from one machine to another. The hardware capabalities of the various machines are summarized in the following table:
| Feature | 11/03 | 11/04 | 11/05,10 | 11/34 | 11/35,40 | 11/60 | 11/45,70 |
| General Registers | 8 | 8 | 8 | 8/9 | 8/9 | 8,9 | 16 |
| Memory Management | no | no | no | yes | yes(O) | yes | yes(O) |
| Processor Modes | 1 | 1 | 1 | 2 | 2 | 2 | 3 |
| Extended Arithmetic | EIS(O),FIS(O) | EAE(O) | EAE(O) | EIS,FPP(O) | EIS(O),FIS(O) | EIS,FPP | EIS,FPP(O) |
| Cache Memory | no | no | no | yes | yes | yes | no(45),yes(70) |
| User Microprogrammable | yes(O) | no | no | no | yes(O) | yes(O) | no |
| Register-to-Register Add | 3.5 us | 3.2 us | 3.7 us | 2.1 us | 1.0 us | .34 us | .30 us |
The "O" designation in the above table means "Optional". The register-to-register add time in microseconds is indicative of processor speed.