## Floating Instruction Set (FIS)

In each instruction below, R contains pointer to a stack of 16-bit words. Each pair of words holds a 32-bit doubleword that contains a floating point value.

 FADD 0 111 101 000 000 rrr
 Operation: [(R)+4, (R)+6] = [(R)+4, (R)+6] + [(R), (R)+2], if result >= 2^-128; else [(R)+4, (R)+6] = 0 Condition Codes: N: set if result < 0; cleared otherwise Z: set if result = 0; cleared otherwise V: cleared C: cleared Description: Adds the A argument to the B argument and stores the result in the A argument position on the stack. General register R is used as the stack pointer for the operation. Symbolic: A = A + B Note: MFPS is not implemented in the PDP-11/60. A processor trap through vector address 10 occurs for reserved instruction.

 FSUB 0 111 101 000 001 rrr
 Operation: [(R)+4, (R)+6] = [(R)+4, (R)+6] - [(R), (R)+2], if result >= 2^-128; else [(R)+4, (R)+6] = 0 Condition Codes: N: set if result < 0; cleared otherwise Z: set if result = 0; cleared otherwise V: cleared C: cleared Description: Subtracts the B argument from the A argument and stores the result in the A argument position on the stack. General register R is used as the stack pointer for the operation. Symbolic: A = A - B Note: MFPS is not implemented in the PDP-11/60. A processor trap through vector address 10 occurs for reserved instruction.

 FMUL 0 111 101 000 010 rrr
 Operation: [(R)+4, (R)+6] = [(R)+4, (R)+6] * [(R), (R)+2], if result >= 2^-128; else [(R)+4, (R)+6] = 0 Condition Codes: N: set if result < 0; cleared otherwise Z: set if result = 0; cleared otherwise V: cleared C: cleared Description: Multiplies the A argument by the B argument and stores the result in the A argument position on the stack. General register R is used as the stack pointer for the operation. Symbolic: A = A * B Note: MFPS is not implemented in the PDP-11/60. A processor trap through vector address 10 occurs for reserved instruction.

 FDIV 0 111 101 000 011 rrr
 Operation: [(R)+4, (R)+6] = [(R)+4, (R)+6] / [(R), (R)+2], if result >= 2^-128; else [(R)+4, (R)+6] = 0 Condition Codes: N: set if result < 0; cleared otherwise Z: set if result = 0; cleared otherwise V: cleared C: cleared Description: Divides the A argument by the B argument and stores the result in the A argument position on the stack. If the divisor (B argument) is equal to zero, the stack is left untouched. General register R is used as the stack pointer for the operation. Symbolic: A = A / B Note: MFPS is not implemented in the PDP-11/60. A processor trap through vector address 10 occurs for reserved instruction.

Don S. Bidulock
Department of Computer Science
University of Calgary
Calgary, Alberta