Department of Computer Science

PDP-11 Processor Handbook

Instruction Set Summary

The specification for each instruction includes the mnemonic, octal code, binary code, a diagram showing the format of the instruction, a symbolic notation describing its execution and the effect on the condition codes, a description, special comments, and examples.

MNEMONIC: This is indicated at the top left corner of each page. When the word instruction has a byte equivalent, the byte mnemonic is also shown.

INSTRUCTION FORMAT: This is indicated at the top right corner of each page. The format is written in binary displaying bit assignments. Note that in byte instructions the most significant bit (bit 15) is always a 1.

SYMBOLS:

() = c contents of

SS or src = source address

DD or dst = destination address

loc = location

<- = becomes

^ = boolean AND

OR = boolean OR

XOR = exclusive OR

~ = boolean NOT

Reg or R = register

B = Byte

Single Operand

	Mnemonic	Description	Octal Op Code
General
	CLR(B)	clear destination	`.050DD`
	COM(B)	complement destination	`.051DD`
	INC(B)	increment destination	`.052DD`
	DEC(B)	decrement destination	`.053DD`
	NEG(B)	negate destination	`.054DD`
	TST(B)	test destination	`.057DD`
Shift & Rotate
	ASR(B)	arithmetic shift right	`.062DD`
	ASL(B)	arithmetic shift left	`.063DD`
	ROR(B)	rotate right	`.060DD`
	ROL(B)	rotate left	`.061DD`
	SWAB	swap bytes	`0003DD`
Multiple Precision
	ADC(B)	add carry	`.055DD`
	SBC(B)	subtract carry	`.056DD`
	SXT	sign extend	`0067DD`
PS Word Operators
	MFPS	move byte from PS	`1067DD`
	MTPS	move byte to PS	`1064SS`

Double Operand

	Mnemonic	Description	Octal Op Code
General
	MOV(B)	move source to destination	`.1SSDD`
	CMP(B)	compare src to dst	`.2SSDD`
	ADD	add src to dst	`06SSDD`
	SUB	subtract src from dst	`16SSDD`
Logical
	BIT(B)	bit test	`.3SSDD`
	BIC(B)	bit clear	`.4SSDD`
	BIS(B)	bit set	`.5SSDD`

Program Control

	Mnemonic	Instruction	Octal Op Code
Branch
	BR	branch (unconditional)	`0004XX`
	BNE	branch if not equal (to zero)	`0010XX`
	BEQ	branch if equal (to zero)	`0014XX`
	BPL	branch if plus	`1000XX`
	BMI	branch if minus	`1004XX`
	BVC	branch if overflow is clear	`1020XX`
	BVS	branch if overflow is set	`1024XX`
	BCC	branch if carry is clear	`1030XX`
	BCS	branch if carry is set	`1034XX`
	SOB	subtract one and branch (if !=0)	`077RXX`
Signed Conditional Branch
	BGE	branch is greater than or equal (to zero)	`0020XX`
	BLT	branch if less than (zero)	`0024XX`
	BGT	branch if greater than (zero)	`0030XX`
	BLE	branch if less than or equal (to zero)	`0034XX`
Unsigned Conditional Branch
	BHI	branch if higher	`1010XX`
	BLOS	branch if lower or same	`1014XX`
	BHIS	branch if higher or same	`1030XX`
	BLO	branch if lower	`1034XX`
Jump & Subroutine
	JMP	jump	`0001DD`
	JSR	jump to subroutine	`004RDD`
	RTS	return from subroutine	`00020R`
	MARK	mark	`006400`
	SPL	set priority level	`00023N`
Trap & Interrupt
	EMT	emulator trap	`104000-104377`
	TRAP	trap	`104400-104777`
	BPT	breakpoint trap	`000003`
	IOT	input/output trap	`000004`
	RTI	return from interrupt	`000002`
	RTT	return from interrupt	`000006`
Miscellaneous
	HALT	halt	`000000`
	WAIT	wait for interrupt	`000001`
	RESET	reset external bus	`000005`
Condition Code Operators
	CLC	clear C	`000241`
	CLV	clear V	`000242`
	CLZ	clear Z	`000244`
	CLN	clear N	`000250`
	CCC	clear all CC bits	`000257`
	SEC	set C	`000261`
	SEV	set V	`000262`
	SEZ	set Z	`000264`
	SEN	set N	`000270`
	SCC	set all CC bits	`000277`
	NOP	no operation	`000240`

Extended Instruction Set

	Mnemonic	Instruction	Octal Op Code
Double Operand Register Group
	MUL	multiply	`070RSS`
	DIV	divide	`071RSS`
	ASH	shift arithmetically	`072RSS`
	ASHC	arithmetic shift combined	`073RSS`
	XOR	exclusive or	`072RDD`

Floating Instruction Set

	Mnemonic	Instruction	Octal Op Code
Double Operand Zero Address Group
	FADD	floating add	`07500R`
	FSUB	floating subtract	`07501R`
	FMUL	floating multiply	`07502R`
	FDIV	floating divide	`07503R`

Don S. Bidulock
Department of Computer Science
University of Calgary
Calgary, Alberta
Canada T2N 1N4
Phone: 403 220-7689 Fax: 403 284-4707
email: dsb@cpsc.ucalgary.ca