Department of Computer Science

PDP-11 Processor Handbook

Instruction Set Summary

The specification for each instruction includes the mnemonic, octal code, binary code, a diagram showing the format of the instruction, a symbolic notation describing its execution and the effect on the condition codes, a description, special comments, and examples.

MNEMONIC: This is indicated at the top left corner of each page. When the word instruction has a byte equivalent, the byte mnemonic is also shown.

INSTRUCTION FORMAT: This is indicated at the top right corner of each page. The format is written in binary displaying bit assignments. Note that in byte instructions the most significant bit (bit 15) is always a 1.


() = c contents of
SS or src = source address
DD or dst = destination address
loc = location
<- = becomes
^ = boolean AND
OR = boolean OR
XOR = exclusive OR
~ = boolean NOT
Reg or R = register
B = Byte

Single Operand

MnemonicDescription Octal Op Code
CLR(B) clear destination.050DD
COM(B) complement destination.051DD
INC(B) increment destination.052DD
DEC(B) decrement destination.053DD
NEG(B) negate destination.054DD
TST(B) test destination.057DD
Shift & Rotate
ASR(B) arithmetic shift right.062DD
ASL(B) arithmetic shift left.063DD
ROR(B) rotate right.060DD
ROL(B) rotate left.061DD
SWAB swap bytes0003DD
Multiple Precision
ADC(B) add carry.055DD
SBC(B) subtract carry.056DD
SXT sign extend0067DD
PS Word Operators
MFPS move byte from PS1067DD
MTPS move byte to PS1064SS

Double Operand

MnemonicDescription Octal Op Code
MOV(B) move source to destination.1SSDD
CMP(B) compare src to dst.2SSDD
ADD add src to dst06SSDD
SUB subtract src from dst16SSDD
BIT(B) bit test.3SSDD
BIC(B) bit clear.4SSDD
BIS(B) bit set.5SSDD

Program Control

MnemonicInstruction Octal Op Code
BR branch (unconditional)0004XX
BNE branch if not equal (to zero)0010XX
BEQ branch if equal (to zero)0014XX
BPL branch if plus1000XX
BMI branch if minus1004XX
BVC branch if overflow is clear1020XX
BVS branch if overflow is set1024XX
BCC branch if carry is clear1030XX
BCS branch if carry is set1034XX
SOB subtract one and branch (if !=0)077RXX
Signed Conditional Branch
BGE branch is greater than or equal (to zero)0020XX
BLT branch if less than (zero)0024XX
BGT branch if greater than (zero)0030XX
BLE branch if less than or equal (to zero)0034XX
Unsigned Conditional Branch
BHI branch if higher1010XX
BLOS branch if lower or same1014XX
BHIS branch if higher or same1030XX
BLO branch if lower1034XX
Jump & Subroutine
JMP jump0001DD
JSR jump to subroutine004RDD
RTS return from subroutine00020R
MARK mark006400
SPL set priority level00023N
Trap & Interrupt
EMT emulator trap104000-104377
TRAP trap104400-104777
BPT breakpoint trap000003
IOT input/output trap000004
RTI return from interrupt000002
RTT return from interrupt000006
HALT halt000000
WAIT wait for interrupt000001
RESET reset external bus000005
Condition Code Operators
CLC clear C000241
CLV clear V000242
CLZ clear Z000244
CLN clear N000250
CCC clear all CC bits000257
SEC set C000261
SEV set V000262
SEZ set Z000264
SEN set N000270
SCC set all CC bits000277
NOP no operation000240

Extended Instruction Set

MnemonicInstruction Octal Op Code
Double Operand Register Group
MUL multiply070RSS
DIV divide071RSS
ASH shift arithmetically072RSS
ASHC arithmetic shift combined073RSS
XOR exclusive or072RDD

Floating Instruction Set

MnemonicInstruction Octal Op Code
Double Operand Zero Address Group
FADD floating add07500R
FSUB floating subtract07501R
FMUL floating multiply07502R
FDIV floating divide07503R

Don S. Bidulock
Department of Computer Science
University of Calgary
Calgary, Alberta
Canada T2N 1N4
Phone: 403 220-7689 Fax: 403 284-4707

University of Calgary