From the very beginning, the designers of the PDP-11 realized that a 16-bit minicomputer with an address space of 32 Kwords was not sufficient. With time, programmers would discover that they needed more memory space, or they would find new ways to use a computer, such as multiprogramming, that would necessitate an expansion of memory and separation (protection) of programs that are co-resident in memory.
The addresses generated by the first PDP-11 processor, the 11/20, were actually 18-bit direct byte addresses. Although the 11/20 word length and operational logic was 16 bits, the UNIBUS addressing logic was actually 18 bits. Thus, while the 11/20 could only address up to 32 Kwords, the bus could address up to 128 Kwords. This was not generally known to programmers, but closer examination would have revealed that all I/O page addresses in the range 160000 to 177777 were actually converted to addresses in the range 760000 to 777777. The extra two bits were "hard-wired" in so that all I/O page addresses had two high order bits always set to one.
With the introduction of the 11/40 and 11/45, 18-bit addressing was made possible so that processor addresses could be modified into 18-bit quantities. Later on with the 11/70 these became 22 bit quantities, with fundamentally the same addressing scheme as for 18 bit addresses.
An option on some PDP-11 systems, and a standard feature on others, the memory management facility is the unit which allows for the extended addressing capability. When the unit is operating, the normal 16-bit direct byte address is no longer interpreted as a physical address, but instead as a virtual address, containing information to be used in the construction of an 18-bit address. The information contained in a virtual address is combined with relocation and description information contained within an Active Page Register (APR) to yield an 18-bit physical address.
The purpose of the APR's is to perform memory relocation and to provide an extended addressing capability for systems with more than 28K of physical memory (there is 4K in the I/O page). There are two sets of page registers in the 11/34, 35, 40, and 60 (more in the 11/45, 55, and 70) which provide memory management when operating in the kernel and user modes, respectively. This allows the operating system to have one set of page registers for its exclusive use, while users share the other set. Indeed, one of the functions of a mutiprogrammed OS is the loading and unloading of memory management registers as users are given the use of the processor through "time-slicing".
Each APR is actually a pair of 16-bit registers, a Page Address Register (PAR) and a Page Descriptor Register (PDR). The PAR contains the starting address where that page is found in memory, and the PDR contains information on the size of the page, how the page may be expanded, and access permissions (read, write, or both) on each page.
The virtual address space the programmer uses is actually divided into 8 pages of 4Kwords each. The first 3 bits of a 16-bit virtual address are used to select one of the APR's. The base address of that page, contained in the PAR, defines where the page begins in the physical address space. For example, if a virtual address for some instruction is 120000, then APR5 (101) is used. If APR5 contains starting address 3200, then the actual physical address becomes 320000.
How does this work out? Since some programs may not require a full 4 Kword page, the PDR allows for variable size pages from 1 to 128 blocks, each block is 32 words, with a maximum of 4096 words. The formation of a physical address is illustrated below:
The logical sequence involved in construction of a physical address is as follows: