Department of Computer Science

PDP-11 Processor Handbook

Addressing Mode Illustrations


General Register Addressing Modes

R is a general register, 0 to 7.
(R) is the contents of register R.
OPR is some single-operand OPeRation.


Mode 0RegisterOPR R R contains operand.


Mode 1 Register
deferred
OPR (R) R contains address.


Mode 2 AutoincrementOPR (R)+ Contents of R are used as address, then increment R. Note that R6 and R7 are always incremented by two.


Mode 3 Autoincrement
deferred
OPR @(R)+ R contains address of address, then increment R by two.


Mode 4 AutodecrementOPR -(R) Decrement R, then R contains address. Note that R6 and R7 are always decremented by two.


Mode 5 Autodecrement
deferred
OPR @-(R) Decrement R by two, then R contains address of address.


Mode 6 IndexOPR X(R) R + X is address. X is contained in the word following the instruction.


Mode 7 Index
deferred
OPR @X(R) R + X is address of address. X is contained in the word following the instruction.


Program Counter Addressing Modes

Register = 7


Mode 2 ImmediateOPR #n Literal operand n is contained in the word following the instruction.


Mode 3 AbsoluteOPR @#A Address A is contained in the word following the instruction.


Mode 6 RelativeOPR A PC + 4 + X is address. PC + 4 is updated PC.


Mode 7 Relative
deferred
OPR @A PC + 4 + X is address of address. PC + 4 is updated PC.


Don S. Bidulock
Department of Computer Science
University of Calgary
Calgary, Alberta
Canada T2N 1N4
Phone: 403 220-7689 Fax: 403 284-4707
email: dsb@cpsc.ucalgary.ca

University of Calgary